Derive an equation that defines the worst case low-high propagation delay for a Static CMOS 4-input NOR gate. Use the Resistor-Switch model to illustrate your answer and state any assumptions made. Using a Static CMOS Resistor-Switch model and the parameters in Table 1, determine the worst case low-high propagation delay for the logic circuit shown in Figure 1. Value 3.29 fF 0.87 fF Parameter Load capacitance Internal node capacitance NMOS device normalised resistance PMOS device normalised resistance NMOS device W/L ratio PMOS device W/L ratio 17 k92 32 k2 0.5/0.35 um 0.4/0.25 um Table 1 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6! > Doutput Figure 1