Design a FSM in VHDL that recognizes two strings 1001 and 0101. Strings overlapped in the input should be recognized. It reads an input, and increment the count whenever either strong is recognized. The interface of the design is given in the table below.

Please include the TESTBENCH used for synthesis. Listing 6.4 below:

1 Description (1) Design a FSM in VHDL that recognizes two strings " 1001" and "0101". Strings overlapped in the input should be recognized. It reads an input, and increment the count whenever either strong is recognized. The interface of the design is given in the table below clock reset din count (7:0)output data output input clock signal input synchronous reset; clear state of count to all '0's input serial input Create a testbench to simulate your deign using the sequence din - 11001010110100100110101010011101. We may simulate your design with more diverse sequences than the one shown above (2) Refer to the binary divider design in Listing 6.4 in Chu's book. Create a VHDL model with a master and a slave communicating with each other. The slave implements the binary division The master generates two numbers which are sent to the slave for division. Once the results returned, the master checks the correctness of the results while producing a new pair of numbers for the slave (a) Development the master and slave with proper interface. In this assignment, the slave should be developed as a synthesizable model, while the master is described a test gener- ation component (b) Connect them in a testbench, and simulate it (c) Simulate your design such that the master and slave can communicate correctly Listing 6.4 Division circuit library ieee; use ieee. std_logic_1164. all; use ieee.numeric std.all; entity div is generic integer := 8; integer CBIT CBIT=log2(W)+1 := 4 - : 130 FSMD clk, reset in std.logic; start port ( 1 downto 0x o 0 : in std.logic; dver, dvnd : in stdlogic-vector( : out std_logic ready done tick out std.logic; quo, rmd: out std.logic-vector(W 1 downt end div type state type is (idle, op, last, done); signal state.reg signal state next signal rh reg, rh.next: unsigned (W -1 downto 0); signal rl.reg, rl.next: std.logic.vector(W - 1 downto 0); signal rh.tmp signal dreg, d.nextunsigned (W 1 downto 0); signal n_reg, n.next unsigned (CBIT 1 downto 0); signal q.bit architecture arch of div is : state.type; : state.type unsigned(W-1 downto 0) : std_logic; in fsmd state and data registers process (clk, reset) begin if reset 1' then state reg ,0'); rl.reg (others-> 0) (others (others ,0'); ,0'); => n.reg ready ,0'); dividend divisor- ri-reg(W rh-tmp ; done; 2 downto 0) state-next done-tick idle; "1"; = ,0'); rl.reg (others-> 0) (others (others ,0'); ,0'); => n.reg ready ,0'); dividend divisor- ri-reg(W rh-tmp ; done; 2 downto 0) state-next done-tick idle; "1"; =