Design a synchronous counter using JK flip-flops that follows the sequence 001,011,101, 111 and repeats. The undesired states will go to do not care stage on the next clock pulse. a) Construct the state diagram for the counter. b) Create the next state table according to the state diagram in (a) [2 Marks] [2 Marks] c) Use J-K excitation table to define the J and K inputs for each flip-flop involved in the counter. [2 Marks] d) Perform K-map simplification for each of the flip-flops in the counter. [2 Marks] e) Implement the simplified expressions as combinational logic using JK flip-flops to complete the design of the counter. [2 Marks]