Design a system having main memory of size 64B (with 4B/block) and cache memory size of 16B, and each cache line is composed of 4 blocks. (a) How many bits are used to address all possible blocks in the main memory? (b) How many blocks are used in main memory? (c) How many bits can be used for a physical address? (d) Design a number of lines in cache memory. (e) How can we address number of lines in terms of bits)? (f) How many bits are used for tag? (g) Explain how many-to-one mapping is possible. While responding, try to draw figures so that they make easy for understanding