Design a Verilog code that represents the circuit shown above with the following specifications:

Inertial delay for xOR$=$ first digit of your ClassID

Inertial delay for $OR=$ Second digit of your ClassID.

Inertial delay for $2-$input AND $=$ Third digit of your ClassID

Transport delay for $w5=3$

Transport delay for $w6=5.$

No delay for all other wires.