Design and implement a Trac Light Controller (TLC) that meets the foll owing specication.

Trac lights are installed on an intersection of a busy highway and a local f arm road. Detectors are installed on the intersection that cause signal Car t o be asserted high in the presence of a car on the farm road approaching the in tersection. In the initial state, the highway lights must be Green (state HG) and the farm road light must be Red (state FR). The lights must remain at this state for at least 3 clock cycles before any change of lights can occur. When a car is detected on the farm road approaching the intersection, the highway lights should cycle from Green (HG) through Yellow (state HY) to Red (state HR), and the farm road light should subsequently turn Green (state FG). Cycling to and from state HY should take one clock cycle each. The farm road lights are to remain Green (FG) only while the signal Car remains high, but no longer than for 2 clock cycles. The farm road lights are then to cycle through Yellow (FY) to Red (FR), at which point the highway lights should turn Green (HG). Cycling to or form farm road Yellow (state FY) also takes one clock cycle. Upon return to the initial state (HG/FR) the highway lights are not to be interrupted again for at least 3 clock cycles. Note: When the light on one road is green or yellow, the light on the other road must be red.

Implementation Details: INPUTS: Your Trac Light Controller circuit has one primary input, Car (car sensor) (for simplicity we are not going to include a Reset signal, which should normally be present in any sequential design produced by a respectable engineer). The design also contains a periodic signal, clock Clk. OUTPUTS: The circuit should have six trac light outputs: three for the highway lights (HG, HY, HR) and three for the farm road lights (FG, FY, FR). These signals can be derived directly from the state registers (which suggests that you should use Moore FSM for your implementation). Synthesize the TLC circuit as a Moore FSM by performing the following tasks: Derive and draw the state diagram for your design. While the number of states depends on your particular approach, you should use as few states as possible. Please use the names used above to create meaningful names for the states, e.g., S0=HG/FR, etc. Encode the states and convert your state diagram to a state transition table; derive the nal implementation with minimum number of logic gates and show the resulting gate-level schematic. (This process is called logic synthesis).