Design in VHDL a 4-bit up-down counter as presented below:

The operation of the up-down counter is described by the following truth table:

S1 S0	Action
0 0	Hold
0 1	Count up
1 0	Count down
1 1	Parallel Load

Provide VHDL code and testbench

CLK X3 X2 X1 XO $1 SO RST Q3 Q2 Q1 QO X3X2X1X0 - Parallel Load $150 - Function Select Input RST- Asynchronous Reset Input CLK-Clock Input Q3Q2Q1Q0 - Parallel Output