Design the following ROM with 2-d addressing ROM for storing the addition table for 2-bit numbers Where xI1] is most significant while x[0] is least significant and y[1] is most significant while y[O] is least significant and z[2] is most significant and z[0] is least significant x, y are inputs z is output a)Fill in the table xI1] x(0] yIO] Z12] ZIO] 0 b) Draw the logic diagram using exactly two 2x4 Decoders, AND gates and OR gates. (You can seperate the outputs into separate logic diagrams if that is clearer to read)