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For TTL NAND gate circuit shown in the figure. 1 below. Given that p = 20 BR = 0.1 Vcc= 5V, VCE (sat) =
For TTL NAND gate circuit shown in the figure. 1 below. Given that p = 20 BR = 0.1 Vcc= 5V, VCE (sat) = 0.2V, VBE (Sat) = 0.8V, VBE (on) = VD = 0.7V,VBEY = 0.5V and Voy = 0.6V. Assumed that Q and Q3 are saturated when all inputs are high. Input A Input B a) Calculate Fan out (N) b) Calculate Logic Swing Figure 1 R 3.5 kn Q R 1.2 Ke R3 0.4 -o +Vcc Re 120 Kes D3 Output 03
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Management Accounting
Authors: Leslie G. Eldenburg, Albie Brooks, Judy Oliver, Gillian Vesty, Rodney Dormer, Vijaya Murthy, Nick Pawsey
4th Edition
0730369382, 978-0730369387
