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** Digital Logic** 2. (a) Design a 3 bits negative triggered asynchronous down counter using D flipflops. Show the flow diagram. (3) (b) Suppose you

** Digital Logic** image text in transcribed

2. (a) Design a 3 bits negative triggered asynchronous down counter using D flipflops. Show the flow diagram. (3) (b) Suppose you have 2 registers A and B. Design a serial subtractor in a way that B - A + A. The result will be saved to A. (3)

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