DIGITAL LOGIC WITH VERILOG DESIGN

PLEASE READ IT WELL I WANT A DRAWING IN BOTH MEALY AND MOORE FOR THIS THEN I WANT FOR IT A VERILOG ON THE MOORE DRAWING. part a: FOR BOTH MEALY AND MOORE

PART A : Derive the state diagram for an FSM that has an input w and an output z. The machine has to generate z = 1 when the previous four values of w were 1001 or 1111; otherwise, z = 0. Overlapping input patterns are allowed. An example of the desired behavior is w : 010111100110011111 z : 000000100100010011

PART B: FOR ONLY MOORE Write Verilog code for the FSM described in Problem 6.3.