Draw circuit (minimum) with 2 input NAND/NOR gates: SOP: H = A POS: H = (A+0)x1 SOP: ) = ADC POS: ) = (C+A)x(C+D) SOP: LE B'C' + A POS: L = (A +C')x(A'+B) IV/ SOP : E = A'D+AD POS : E = (A+D)x(A'+D')