Dynamic Partial Reconfiguration enables the exchange of logic partitions, called Reconfigurable Partitions $($RP$),$ within the FPGA fabric. Thereby, the system can be adapted for an optimized execution according to the application, as well as the application phase. This is a major advantage for designing efficient hardware architectures able to adjust the hardware due to characteristics of special types of ANNs. Moreover, the integration of DPR enables the exploration of dynamic adaptations, for instance in growing neural networks or reinforcement learning. However, similar to ASIC development, designing FPGA implementations is more complex in comparison to software development. Therefore, there is a need to develop a design flow, enabling a semi$-$automated impl