Examine how latencies of individual components of the datapath affect the clock cycle time of the entire datapath, and how these components are utilized by instructions

	I-Mem	Add	Mux	ALU	Regs	D-Mem	Sign-Ext	Shift Left
ps	230	80	20	100	95	270	15	10

requirement:

1. What is the clock cycle time if the only types of instructions we need to support are ALU instructions (ADD, AND, etc.)?
2. What is the clock cycle time if we only have to support LW instructions?
3. What is the clock cycle time if we must support ADD, BEQ, LW, and SW instructions?

IF/ID ID/EX EX/MEM MEM/WB > Add Shift left 2 Add Add result PC Address Read register 1 Read Read data 1 register 2 Instruction memory Registers Read Zero ALU ALU result Address Read data data 2 Write register Write data Data memory Write data 16 Sign- extend