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Fig. 3 . 1 2 2 5 6 B memory bank example 3 . 3 Figure 3 . 1 2 shows two memory banks being

Fig.
3
.
1
2
2
5
6
B memory bank example
3
.
3
Figure
3
.
1
2
shows two memory banks being used for connection with a
1
6
-
bit
data bus, one bank set for the even numbered addresses and the other for the
odd numbered addresses.
a
.
What would happen if the least significant address line from the micro
-
processor is connected to the least significant address line in both banks?
b
.
How would you solve the problem presented in
(
a
)
?

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