FIGURE $4\mathrm{.}35$ The pipelined version of the datapath in Figure $4\mathrm{.}33.$ The pipeline registers, in color, separate each pipeline stage.

They are labeled by the stages that they separate; for example, the first is labeled $I\frac{F}{\text{I}}D$ because it separates the instruction fetch and instruction

decode stages. The registers must be wide enough to store all the data corresponding to the lines that go through them. For example, the

IF$/$ID register must be $64$ bits wide, because it must hold both the $32-$bit instruction fetched from memory and the incremented $32-$bit PC

address. We will expand these registers over the course of this chapter, but for now the other three pipeline registers contain $128,97,$ and $64$

bits, respectively.

FIGURE $4\mathrm{.}50$ The control lines for the final three stages. Note that four of the nine control lines

are used in the EX phase, with the remaining five control lines passed on to the EX$/$MEM pipeline register

extended to hold the control lines; three are used during the MEM stage, and the last two are passed to MEM$/$

$WB$ for use in the WB stage.