Find data hazard and draw the pipeline cycles for both without and with forwarding. Lwrl, 0(rl) And rl, rl, r2 Lw 12, 0(rl) Lw rl, 0(r3) Problem 5: If there is only one memory then indicate what kind of hazard and show in pipeline diagram, how to remove this hazard. Sw r16, 12(16) Lw r16, 8(16) Beq r5, r4, label: Assume r5 != r4 Add r5, rl, r4 Slt r5, r15, r4