Find the overall worst-case delay (i.e. the delay at which all the outputs of the circuit are finalized) for each of the unsigned adder circuits mentioned below (carry-in to the first bit position=0 in each case). Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in unless specified otherwise. i. 16-bit block CLA (BCLA) with block size=8 ii. 16-bit block CLA (BCLA) with block size=4 iii. 16-bit block RCA-BCL adder with block size=8 iv. 16-bit block RCA-BCL adder with block size=4 v. 16-bit block carry-skip adder (CSA) with block size=2 vi. 16-bit block carry-select adder (CSelA) with block size=4. Assume that the first block is implemented as an RCA