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For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag Index Offset 31-10
For a direct-mapped cache design with a 32-bit address, the following bits of the address are
used to access the cache.
Tag | Index | Offset |
31-10 | 9-4 | 3-0 |
a) How many bits are required for the cache implementation (only consider tag + data)
b) How many bits can be stored as data in the cache (only consider data) ?
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