For each of the signed adder/subtractor circuits mentioned below, find the overall worstcase delay (i.e. the delay at which all the outputs of the circuit are finalized). Assume that the core unsigned adder is implemented using RCA logic in each case. Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in.

i. 8-bit 1s complement adder/subtractor

ii. 8-bit 2s complement adder/subtractor