For the

following circuit with the given state assignment, find a clocked JK flipflop implementation. Write the logic equations and sketch the logic diagram.

\begin{tabular}{cc|cc} Q(t) & Q(t+) & S(t) & R(t) \\ \hline 0 & 0 & 0 & d \\ 0 & 1 & 1 & 0 \\ 1 & 0 & 0 & 1 \\ 1 & 1 & d & 0 \end{tabular} \begin{tabular}{cc|ccc} y1 & y0 & & 0 & 1 \\ \hline 0 & 0 & A & A/0 & B/1 \\ 0 & 1 & B & B/1 & C/1 \\ 1 & 1 & C & C/1 & A1 \end{tabular}