For the following questions, assume that the memory system uses byte addressable that are 32-bit long. In addition, assume all data words in such memory consists of 4-bytes (32-bits). Answer the following questions: Design a 4-way set associative cache that can store 1 M byte of data. Assume each cache block consist of 8 data words. Make sure to indicate the total number of cache sets, size of tag/data field, and which part of the address is used as tag and cache set selection. In addition, show all wirings needed to identify the hits and the section of appropriate set/word in the cache. What is the total number of bits needed to implement the cache if it has valid and dirty bit fields? Show your work. Given the following memory byte addresses, identify whether it is a hit or a miss assuming an initially empty cache: 0D (00000000H), 671090688D (28000800H), 24D (00000018H), 671088664D (28000018H), 13421774D (28000040H) Assume the cache uses an LRU replacement algorithm. In addition, show the final content of cache for the given address sequence