For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses data. What is the total execution time of this instruction sequence in the 5-stage pipeline that only has one memory? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? Why?

In this exercise, we examine how resource hazards, control hazards, and ISA design can affect pipelined execution Problems in this exercise refer to the following fragment of MIPS code: Instruction sequence SW R2, 0 (R3) OR R1, R2 R3 Label Assume R2 R0 BEQ R2 R0 OR R2 R2, RO Label: ADD R1, R4, R3