Generator "running 0 " on the D-flip-flops

Similarly to the shift register in Figure 1, but the output Q4 is connected to the input data of the first discharge (DATA). The first trigger sets to "0" when reset=0 , and all another triggers sets to "1".

4 bit

structural

Please i need the vhdl code and testbench code for this task

please include a screenshot of the timing diagram

thank you