Verilog is one of the ways to model hardware using a .description programming language :Select one True False In a UDP, how many outputs are allowed to be :listed in the port list ? Select one .a .Depends on the design .b .C 1 .d equal to the number of inputs Consider the following code, which one of the ?following statements is not true ;(module circuit(out, A, B, s ;output out ;input A, B ;input s ;assign out =(s)? A :B :endmodule Select one .a .Dataflow modeling is used .b There are no false statements in the given options .C The code represents a combinational .circuit .d .Ternary operators are used The circuit represents a 2 to 1 line multiplexer