give me the verilog code and test code for the following Q Q$4$: Design a one$-$input, one$-$output serial $2\text{'}$s complementor. The circuit accepts a string of

bits from the input and generates the $2\text{'}$s complement at the output. The circuit can be

reset asynchronously to start and end the operation.

Test your circuit using the following input sequence.

$010111110111100$

Random sequence of your choice.