Given the following ASM Chart: TO S TI - Input B Input2 Input3 0 T2 A AB T3 Z 0 T4 SHR B by 1 blt SHR N by 1 bit TS D:XOR SHR: Shin Right A: 16 bits Storage Register EN: 16 bits Shin Registers No The Least Sigulfcant Bit of N 7: The zero signal is set to (1) when the value of shift reghter Nis Zero 1) Design the data processor (You have to show the data source and the control signals for each component. (10 Points) 2) Design the controller using one flip-flop per state (You have t show the clock and the reset signals) (5 Points)