The pipelined MIPS processor is running the following program.

Which registers are being written, and which are being read on the fifth cycle?

addi $s1, $s2, 5 sub $t0, $t1, $t2 lw $t3, 15($s1) sw $t5, 72($t0) or $t2, $s4, $s5

So thats the problem, I understand what the code is doing but what are the registers being written and which ones are on the fifth cycle? Kind of confused.