Given the following, fill in the table below

ALU Register File R_destination(1:0)R_addr_a R_data_a R_source(1:0) R_addr_b R_data_b Output_A[7:0) Output_B[7:0] a F W_data W_addr W_enable R_destination[1:0) - '1' b Input(7:0) 1 use_input Opcode(2:0) Opcode Operation 000 F = b 001 F = a*b (bitwise xor) 010 F = a & b (bitwise and) 011 F = a b (bitwise or) 100 F = a + b (addition) 101 F = a - b (subtraction)** 110 Fra >> 1 (logical shift right) 111 Fra * b (multiplication) Machine Code Register Operation Description Opcode use_input 0 Rd