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Lab #3: Mealy Sequential Circuit 1. Requirement Design a Mealy Sequential Circuit which investigates an input sequence X and which will produce an output of Z 1 for any input sequence 001 has occurred at least once. See table below for a sample set of input sequence. A reset signal RST will reset the circuit (reset the circuit to the initial state). or any input sequence ending in 1010, provided that the Mealy Sequential Circuit RST CLK 2. Pre-lab . State graph . State table