HELP!

Using the following state transition diagram with 6 states (Q2Q100) with 1 input, X, and 1 output, Z: 01 0 100 101 a) Complete the timing trace assuming each column is a new clock edge. (8 pts) X 0 02 10 Q10 Q0 0 Z b) Complete the following state transition table by designing the synchronous machine using a D flip-flop for the Q2 bit, a T flip-flop for the Q1 bit, and a JK flip-flop for the Q0 bit. The first row has been completed for you. (10 pts) X Q2 Q1 Q0Q2+ Q1* Qo* Z D2 Ti JOKO 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0101 | 0110 0111 1000 1001 0 1 0 011 1 1 0 0 1 0 1 1 1 0 1 1 1 1 c) Is the above machine a Mealy or a Moore machine? (1 pt) d) Write the output Q2* in the numerical shorthand sum-of-products form. (2 pts) e) Write the output 01 in the numerical shorthand product-of-sums form. (2 pts) f) Write the output Q0+ in the canonical sum-of-products form. (2 pts) 8) Design the input circuit logic to the D flip-flop for the Q2 bit using an 8:1 multiplexer. (5 pts) h) Design the input circuit logic to the T flip-flop for the Q1 bit using a single 4:16 permanently enabled active-high decoder and a single multi-input OR gate with a size of your choosing. (5 pts) 1. Design the J and K input circuit logic to the JK flip-flop for the Q0 bit using a PROM chip. (5 pts) XX' Q2 Q2 QI QI' QO 20% 1) Design the circuit logic for the Zoutput using the flip flop outputs and NAND gates only. (5 pts)