Here is the code we were provided.

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////////

// Company: // Engineer:

// //

// Design Name:

// Module Name: ROM

// Project Name: // Target Devices: NEXYS-4 Board

// Tool Versions:

// Description:

// // Dependencies: // // Revision:

// Revision 0.01 - File Created // Additional Comments: A is slide switch 15,14,13,12,11, LED 7:0 are the outputs

// Outputs are always displayed for the current address in A using LED's 7:0 D is slide switch 7:0 //////////////////////////////////////////////////////////////////////////////////

module ROM(

output [7:0] LED,

output [4:0] Ao,

input [7:0] D,

input [4:0] A,

input Clear,

input Load

);

reg [7:0] Store [0:31];

initial begin //Can make simpler with a for loop

Store[0]

Store[1]

Store[2]

Store[3]

Store[4]

Store[5]

Store[6]

Store[7]

Store[8]

Store[9]

Store[10]

Store[11]

Store[12]

Store[13]

Store[14]

Store[15]

Store[16]

Store[17]

Store[18]

Store[19]

Store[20]

Store[21]

Store[22]

Store[23]

Store[24]

Store[25]

Store[26]

Store[27]

Store[28]

Store[29]

Store[30]

Store[31]

//put your code here, use an always block to check for load & clear at addressed location

endmodule

DSD F18 Lab In this lab you will design a Verilog Module for a ROM The rom needs to be able to hold 32 unsigned Integers each 8 Bits. Thus it must have 5 address lines 25 32. This seems to be fairly straight forward to do; however, when I wrote this lab code last year and looked at the elaborated schematic post synthesis I was shocked. It was very complicated and did not work very well. I had implemented the design without a clock, since it is a combinational part and really does not need a clock. But, the implementation was horrendous and it did not work quite like it should, so I added a clock to control the update with the address lines and the parallel load. Bam, everything was now very happy, so here is how you can do this with a clock. First set up the rom with this statement reg [7:0] Store [0:31]; //Note the 8 bit words organizes hi-lo Left to Right but the rows organized 0 to 31 Left to Right. You can order the rows opposite if you want, but this makes most sense to me. The columns really do need to be in normal byte order though. Functionally, the ROM should have 1. A parallel Load function using the 8 bit values set in the slide switches 7:0 labeled as D 7:0 in the port list and in the constraint file and pressing the Left button to latch in the data to the ROM. 2. A Clear that should zero the contents of 1 byte that is addressed as described below when the Right button is pressed 3. Address lines to address each of the 32 locations in the "ROM", using the high 5 slide switches, switch 15:11 which are called A 4:0 in the port list and in the constraint file 4. As the address lines are set, the address should display in the high 5 LED 15:11, called Ao 4:0 in the port list and the constraint file and the contents of the ROM at that address should also display as noted below 5. Whatever address is input, the low 8 leds, LED 7:0 should display the value stored in the ROM at the addressed location 6. And finally, use a clock to trigger a real always block to make the Vivado's synthesizer happy 7. Write your own test bench for this project. Have it put a few values into the ROM and see if they are stored. Fill out the questions and paste in your code for turn in as well as have TA sign off on your demo of the solution on the NEYS4 board I have provided the shell only so that everyone can use the same signal names to make following code and debug easier for TA's and me, but stil1 have to write their original solution. So use the shell and finish the code. The shell uses a bunch of statements in the initial block to clear the array variables to zeros. This can be done more simply by using a for loop, just don't forget to initialize the for index variable as an integer variable as shown below: for (i-0; -32; H) remember there is no itt syntax allowed DSD F18 Lab In this lab you will design a Verilog Module for a ROM The rom needs to be able to hold 32 unsigned Integers each 8 Bits. Thus it must have 5 address lines 25 32. This seems to be fairly straight forward to do; however, when I wrote this lab code last year and looked at the elaborated schematic post synthesis I was shocked. It was very complicated and did not work very well. I had implemented the design without a clock, since it is a combinational part and really does not need a clock. But, the implementation was horrendous and it did not work quite like it should, so I added a clock to control the update with the address lines and the parallel load. Bam, everything was now very happy, so here is how you can do this with a clock. First set up the rom with this statement reg [7:0] Store [0:31]; //Note the 8 bit words organizes hi-lo Left to Right but the rows organized 0 to 31 Left to Right. You can order the rows opposite if you want, but this makes most sense to me. The columns really do need to be in normal byte order though. Functionally, the ROM should have 1. A parallel Load function using the 8 bit values set in the slide switches 7:0 labeled as D 7:0 in the port list and in the constraint file and pressing the Left button to latch in the data to the ROM. 2. A Clear that should zero the contents of 1 byte that is addressed as described below when the Right button is pressed 3. Address lines to address each of the 32 locations in the "ROM", using the high 5 slide switches, switch 15:11 which are called A 4:0 in the port list and in the constraint file 4. As the address lines are set, the address should display in the high 5 LED 15:11, called Ao 4:0 in the port list and the constraint file and the contents of the ROM at that address should also display as noted below 5. Whatever address is input, the low 8 leds, LED 7:0 should display the value stored in the ROM at the addressed location 6. And finally, use a clock to trigger a real always block to make the Vivado's synthesizer happy 7. Write your own test bench for this project. Have it put a few values into the ROM and see if they are stored. Fill out the questions and paste in your code for turn in as well as have TA sign off on your demo of the solution on the NEYS4 board I have provided the shell only so that everyone can use the same signal names to make following code and debug easier for TA's and me, but stil1 have to write their original solution. So use the shell and finish the code. The shell uses a bunch of statements in the initial block to clear the array variables to zeros. This can be done more simply by using a for loop, just don't forget to initialize the for index variable as an integer variable as shown below: for (i-0; -32; H) remember there is no itt syntax allowed