I am currently struggling and need help on 7.4 only.

CLK CLK WES WE PC PC A1 RD1 RD A RD Data Instruction A2 RD2 A3 Register WD3 File R15 WD Figure 7.2 Fetch instruction from memory CLK CLK 19:16 RA1 WE3 WE A1 RD1 A RD Data Instruction A2 RD2 A3 Register WD3 File R15 WD Figure 7.3 Read source operand from register file CLK CLK WES WE PC PC A1 RD1 RD A RD Data Instruction A2 RD2 A3 Register WD3 File R15 WD Figure 7.2 Fetch instruction from memory CLK CLK 19:16 RA1 WE3 WE A1 RD1 A RD Data Instruction A2 RD2 A3 Register WD3 File R15 WD Figure 7.3 Read source operand from register file