I have a verilog question.

I have a single and gate(g1) acting as a two-bit even number detector. Inputs: A1, A0. Output: Z

Verilog:

(Everything before this is given)

module even(

input A1, A0,

output Z

);

and g1(Z, ~A1, A0);

endmodule

I'm not sure why this doesn't work. I'm very new to verilog so please explain like I'm five.