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I need to have the answer illustrated within the circuit. I have been provided with an example that demonstrates the similarities of what I need,
I need to have the answer illustrated within the circuit. I have been provided with an example that demonstrates the similarities of what I need, along with the circuit for this work.
points Consider the following singlecycle MIPS processor. For each of the three given instructions, do the following tasks:
Specify the MIPS fields opcode, rs rt rd shamt, funct, immediateoffset
Annotate the diagram by specifying the value of each blue and black wire,
Highlight the active datapaths involved in the instruction.
a points lw $t$s assuming that PC value is X $s contains X and address XC contains the word X
b points beq $s $s ELSE assuming that PC value is X $s contains X $s contains X and ELSE labels an instruction that is placed instructions before the current instruction.
c points sub $s $t $t assuming that PC value is X $t contains X and $t contains X
points Assuming that the opcodes of BEQ and BNE instructions are and respectively, redraw the above diagram so that the resulting circuit can handle both BEQ and BNE instructions currently it is designed to handle BEQ only Hint: Assume that "Branch" output of "Control" unit gets asserted for both BEQ and BNE. To distinguish BEQ and BNE, you can get help from Instruction which is zero for BEQ and one for BNE.
points Assuming that the following numbers show the delay of different circuits participating in the above architecture,
a points Calculate the overall delay of running a LW instruction
b points Calculate the overall delay of running a BEQ instruction.
c points Calculate the maximum clock rate that we can assign to this processor based on the numbers calculated in parts a and b
Instruction Memory: ps
Data Memory: ps
Register File: ps
ALU: ps
Signextend: ps
ShiftLeft : ps
Mux: ps
Adders: ps
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