I tried answering part (a) for the following question. Please provide the answers to (b), (c), (d), and (e). I know Chegg policy says to ask one question, but these are inclusive, as in all part of one question. Thank you in advance.

Answer to (a):

The following sequential logic circuit is a latch. Its inputs are A & B, and its outputs are C and C'. C and C should opposing values: C= NOT(C). a) Generate a truth table for the latch (hint: similar to lecture, find a known state that doesn't depend on the previous output to begin your analysis). b) Generate a timing diagram for the latch (it should cover all possibilities discussed in your truth table) c) Can you identify any actions" for this latch? Label them on your truth table and timing diagram d) Compare this latch to the RS Latch; list their similarities and differences e) Implement this latch using CMOS transistors. You must show all wires to get full credit (feedback wires are the most important!) C' B Latch C c' B Truth Table C Cnext c'next O Latch 1 No change ) latus o ) 0 j , set o 1 7se ] 0 1 j Reset 1 o 1 X no possible Indetermine 1 X X The following sequential logic circuit is a latch. Its inputs are A & B, and its outputs are C and C'. C and C should opposing values: C= NOT(C). a) Generate a truth table for the latch (hint: similar to lecture, find a known state that doesn't depend on the previous output to begin your analysis). b) Generate a timing diagram for the latch (it should cover all possibilities discussed in your truth table) c) Can you identify any actions" for this latch? Label them on your truth table and timing diagram d) Compare this latch to the RS Latch; list their similarities and differences e) Implement this latch using CMOS transistors. You must show all wires to get full credit (feedback wires are the most important!) C' B Latch C c' B Truth Table C Cnext c'next O Latch 1 No change ) latus o ) 0 j , set o 1 7se ] 0 1 j Reset 1 o 1 X no possible Indetermine 1 X X