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Scenario

Consider the architecture of Figure $1.$ The code for execution is summarized by Table $1$

and takess the form of a loop. Assume that such an architecture supports dual issue and a

BTB has been previously seeded with the correct NPC for branch taken. The corresponding

depth for each of the $($pipelined$)$ execution stages is summarized as follows:

FP division $-6$ stages.

FP multiplication $-4$ stages.

FP addition $/$ subtraction $-3$ stages.

Integer or address unit $-1$ stage.

You should also assume that the ALU $($not shown in Figure $1)$ is supported by the same

CDB and Reorder Buffer but has its own set of reservation stations. This means that integer

instructions are executed on the ALU and address calculations are made in the 'Address

Unit':

Question

Complete the timing diagram for the execution of the first two loops, assuming that

the branch is correctly predicted as taken on each loop.

Which instruction produces the most critical dependencies in this example?

How many cycles of each loop are executed speculatively?

What hazard will be the principle hazard that is likely to limit execution under this

example?

Table $1$: Content of looping code