II. Consider the following Boolean fiunctions: F1(A, B, C)-B.C+A", B '. F2( A, B, C ) = B ' . C +A", B ' + A, B, C ' Implement Fl and F2 using one 3:8 Decoder module and two OR gates. (i) (ii) Implement Fl and F2 using two 4:1 Multiplexers and one optional NOT gate. (ii) Implement Fl and F2 using a PLA which has 3 inputs, 2 outputs and 4 products. Show the PLA logic using the notation as per Figure 1.35, page 44 of your text