III. Figure below shows a simplified timing diagram for a DRAM read operation over a bus. The access time is considered to last from t1 to t2. Then there is a recharge time, lasting from t2 to t3, during which the DRAM chips will have to recharge before the processor can access them again. Assume that the access time is 50 Hs (micro seconds) and the recharge time is 300s. Constructing a 64 -bit wide memory system using these