In a computer with a pipeline execution and instruction length between 1 and 4 bytes, the operation code consists of 4 bits. It is decoded by a decoder and fed to an arithmetic-logic device for execution. The decoder is

a.

4:32 decoder

b.

1 of 4 demultiplexer

c.

4:3 decoder

d.

multiplexer 4 to 1

e.

3:4 decoder

f.

a sequential logic circuit

g.

4:16 decoder