In addition, compute the delays C1, C2, C3 and in general Cn when the design of an adder is completed as a carry-lookahead adder as given in Figure 5.2.2 for the case of a 4-bit carry lookahead adder. Assume the gate delays are 2 ns, for AND and OR gates (independent of the number of inputs) and 3 ns for XOR gates. o ?? S3 CARRY PO P2 C3 S2 B2 B CARRY C2 Pl 8 CARRY G1 Ci PO AO BO GO