In our first project, we use the following RISC instructions as the target language of our compiler. The compiler uses the convention (code shape) that every computed or loaded value is copied into a "fresh", virtual register. In the backend of a compiler, these virtual registers have to be mapped" to physical registers, since an executable machine code can only contain the limited set of physical register names of the target machine architecture. instr. format description semantics memory instructions load constant value cinto register r load I c rar C loadAI rar, c load value of MEM( T+ c) into r Tu MEM(rar+ c) storeAI rar ru, c store value in rinto MEM(rut c) arithmetic instructions add contents of registers raand ru, and add rare ru store result into register rz subtract contents of register rafrom register sub ry, and store result into register rz mult ran, ru multiply contents of registers Frand r and rz ry store result into register rz divide contents of registers raand ru, and div r Store result into register rz I/O instruction write value of MEM(rr+ c to standard output print( MEM(ra+ c) output AI r c In our first project, we use the following RISC instructions as the target language of our compiler. The compiler uses the convention (code shape) that every computed or loaded value is copied into a "fresh", virtual register. In the backend of a compiler, these virtual registers have to be mapped" to physical registers, since an executable machine code can only contain the limited set of physical register names of the target machine architecture. instr. format description semantics memory instructions load constant value cinto register r load I c rar C loadAI rar, c load value of MEM( T+ c) into r Tu MEM(rar+ c) storeAI rar ru, c store value in rinto MEM(rut c) arithmetic instructions add contents of registers raand ru, and add rare ru store result into register rz subtract contents of register rafrom register sub ry, and store result into register rz mult ran, ru multiply contents of registers Frand r and rz ry store result into register rz divide contents of registers raand ru, and div r Store result into register rz I/O instruction write value of MEM(rr+ c to standard output print( MEM(ra+ c) output AI r c