In this lab, you will design the $32-$bit Arithmetic Logic Unit $($ALU$).$ It is described in Section $5\mathrm{.}2\mathrm{.}4$

of the text, but you will design the ALU described in the video lectures and lecture notes. Your

ALU is an important building block of microprocessors. In this lab you will design an ALU in

SystemVerilog. You will also write a SystemVerilog testbench and testvector file to test the ALU.

The design in this lab will demonstrate the ways in which SystemVerilog encoding makes

hardware design more efficient. It is possible to design a $32-$bit ALU from $1-$bit ALUs $($i$.$e$.,$ you

could program a $1-$bit ALU incorporating your full adder from Lab $1,$ chain four of these together

to make a $4-$bit ALU, and chain $8$ of those together to make a $32-$bit ALU.$)$ However, it is

altogether more efficient $($both in time and lines of code$)$ to code it succinctly in SystemVerilog.

You will complete the following steps in this lab:

Design an ALU in SystemVerilog

Write a testbench and testvector file to test your ALU

Simulate your ALU using your testbench and testvector file in ModelSim

Create a wrapper module for your ALU $($that maps the ALU interface to the DE$2-115$ board

peripherals$)$

Synthesize $/$ compile ALU in Quartus II $-$ and optimize ALU design if needed

Submission Instructions

Remember that you must always simulate your SystemVerilog design before building it in

hardware.

Be sure to read the "What to Turn In$"($Section $4)$ at the end of the lab before beginning the lab.

Important: Most everyone should be currently enrolled in CpE $200.$ If you are not currently

enrolled in CpE $200($i$.$e$.,$ you took it in a prior semester$),$ you may view the videos, lecture

slides, and example SystemVerilog files on CPE $200$L$\text{'}$s Canvas page.

As always, be sure to start and finish the lab early so that you have enough time to work through

your issues and$/$or have time to ask for help.

DESign AN ALU IN SYStEMVERILOG

Create a $32-$bit ALU in SystemVerilog. Name the file

alu.sv$.$ It should have the following module

declaration:

module alu$($input logic $[31$:$0]$ A$,$ B$,$

input logic $[2$:$0]$ ALUControl,

output logic $[31$:$0]$ Result$)$;