In Verilog HDL

TOP LEVEL DESIGN The top level design will be comprised of the 32-bit counter that wili have its 32 outputs broken into our groups of eight and feed an 8-bit wide 4:1 mux. The mix will require 2 select bits. Our select bits will come from switches and the e 2 Select reset R Count[31:241 dk Count 23:16 Count 15:8 Counti7:0] 8 LEDs outputs will go to the LEDs on the board. 0 DEVELOPMENT First create the design above using Verilog. Then create a test bench as identified below and then simulate the design to ensure it behaves as expected TOP LEVEL DESIGN The top level design will be comprised of the 32-bit counter that wili have its 32 outputs broken into our groups of eight and feed an 8-bit wide 4:1 mux. The mix will require 2 select bits. Our select bits will come from switches and the e 2 Select reset R Count[31:241 dk Count 23:16 Count 15:8 Counti7:0] 8 LEDs outputs will go to the LEDs on the board. 0 DEVELOPMENT First create the design above using Verilog. Then create a test bench as identified below and then simulate the design to ensure it behaves as expected