In verilog, we always need to watch out for the bit-width of each signal. module top_module (); reg clk=0; always \#5 clk = -clk; // Create clock with period =10 initial 'probe start; // Start the timing diagram "probe(clk); // Probe signal "clk" // A testbench reg [7:0] in=8'd0, flip =1b0; wire [7:0] out; initial begin \#10 in 8h5A; \#10 flip =1b1; \#10 in =8 b b1100 0111; \#10 flip