JK Flip-Flop Component Name(s)[print] The textbook shows a logic diagram for how a JK flip- flop may be constructed from a D flip and some ad- ditional NOT, AND, and OR gates. Fortunately, the JKFF is useful enough that monolithic chips with mul- tiple JKFFs have been made. The 74-73 is a dual JKFF chip with independent reset and clock inputs (but no preset) for each flip-flop. Note the non- standard power and ground pin locations! Once again, the reset inputs are active low. 1. Build the circuit shown in TinkerCAD. An appro- priate activity has been provided. This bread- board circuit will be graded as part of this worksheet. 2. To complete the characteristic table, you may need to reset (0) the current state of Q, if it is in the incorrect state for the next table entry. To do this, make the appropriate switch LOW, then switch it back to HIGH. 3. Using the reset input as necessary to set Q(t) if needed, complete the first blank column in the characteristic table. Since the 74-73 does not pro- vide a preset input, you will not be able to go through the table in order, but it is possible to 0,1 J K Q(t) Q(t+1) 0 0 0 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 0 0 1 1 0 1 complete the entire table. The cells will be 0 or 1, shown by the output LED on the output pin. 4. Next, go through the table rows pairwise, and identify each Q(t+1) pair as either 0, 1, Q(t), or Q(t). S7 PLO S6 C ~1Q 14 13 1 2 DI 14 1 3 74-73 Dual JKFF 7 1CLK 1RST 1K w PWR 0,1,Q(t), Q(t) Q(t+1) J GND 74LS73 Y K SO 2CLK2K 2RST2Q IR ~ Q co2Q DI 2JQ- Score 12 13 L7 L6