Question: library ieee; use ieee.std _ logic _ 1 1 6 4 . all; use ieee.numeric _ std . all; entity fsm is generic ( WIDTH

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fsm is
generic (
WIDTH : positive :=16);
port (
clk : in std_logic;
rst : in std_logic;
go : in std_logic;
done : out std_logic;
n_en : out std_logic;
output_en : out std_logic;
k_en : out std_logic;
k_sel : out std_logic;
square_en : out std_logic;
square_sel : out std_logic;
square_lt_n : in std_logic);
end fsm;
architecture default_arch of fsm is
begin -- default_arch
end default_arch; ---FOR fsm.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity datapath is
generic (
WIDTH : positive
);
port (
clk : in std_logic;
rst : in std_logic;
n : in std_logic_vector(WIDTH-1 downto 0);
output : out std_logic;
n_en : in std_logic;
output_en : in std_logic;
k_en : in std_logic;
k_sel : in std_logic;
square_en : in std_logic;
square_sel : in std_logic;
square_lt_n : out std_logic
);
end datapath;
architecture default_arch of datapath is
begin
end default_arch;----for datapath.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity is_perfect_square is
generic (
WIDTH : positive :=16);
port (
clk : in std_logic;
rst : in std_logic;
go : in std_logic;
done : out std_logic;
n : in std_logic_vector(WIDTH-1 downto 0);
output : out std_logic);
end is_perfect_square;
architecture FSMD of is_perfect_square is
begin -- FSMD
end FSMD;
architecture FSM_D of is_perfect_square is
begin
end architecture FSM_D;
architecture default_arch of is_perfect_square is
begin
-- NOTE: Change the architecture here to synthesize/simulate each implementation.
TOP : entity work.is_perfect_square(FSMD)
generic map(
WIDTH => WIDTH
)
port map(
clk => clk,
rst => rst,
go => go,
done => done,
n => n,
output => output
);
end default_arch;
--for is_perfect_square.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity is_perfect_square_tb is
end is_perfect_square_tb;
architecture default_tb of is_perfect_square_tb is
begin
end default_tb;
--for is_perfect_square_tb .vhd
library ieee; use ieee.std _ logic _ 1 1 6 4 .

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