library IEEE use IEEE.STD LOGIC1164 ALL entity hw11 p1 is Port (signal A C: in STD LOGIC; signal signal n4, ins, in2, in1, inO : in STD-LOGIC; mux out: out STD LOGIC); end hw11 pi; architecture behavioral of hw11_plis begin process (A, B, C, in7 -in3, in2, int, ind) is begin case std logic vector(A,B,C) is when "000" mux outcino; when "001" > mux out G when "010" => mux-out when "011"-> mux-outin3; when "100"-> mux out mux-out mux-out <. when others>mux out c in7: end case 111 end process; end behavioral; 2) Rewrite the VHDL code above using a case statement to represent a 4-to-1 MUX with select inputs A, B and input in3, in2, in1, inO. The output is mux out