LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

...

1. Write the receiver VHDL module. call this module "receiver".

2 .Explain what the transmitter, channel, and receiver module do?

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY transmitter IS PORT tx_data tx_sea END transmitter; : IN : OUT STD LOGIC VECTOR( 7 DOWNTO 0); STD_LOGIC_VECTOR ( 8 DOWNTO 0)); ARCHITECTURE structural OF transmitter IS SIGNAL parity : STD_LOGIC; BEGIN -- generate the even parity bit parity