library IEEE;use IEEE.std$\_$logic$\_1164.$all;use IEEE.std$\_$logic$\_$unsigned.all;entity divider is port$($ CLK : in std$\_$logic; A$,$ B : in std$\_$logic$\_$vector$(3$ downto $0)$; Q$,$ R : out std$\_$logic$\_$vector$(3$ downto $0))$;end divider;architecture Behavioral of divider isbegin process$($CLK$)$ variable temp : std$\_$logic$\_$vector$(3$ downto $0)$; variable count : std$\_$logic$\_$vector$(3$ downto $0)$; begin if rising$\_$edge$($CLK$)$ then temp :$=$ A; count :$="0000"$; while temp $>=$ B loop temp :$=$ temp $-$ B; count :$=$ count $+1$; end loop; Q count; R temp; end if; end process;end Behavioral;